In the modern integrated circuit industry, there is a class of integrated circuits known as microcontrollers or "system-on-a-chip" devices. These devices are manufactured and designed to contain embedded core data processors wherein this embedded core communicates with peripherals, memory, or other circuitry on the same substrate. The embedded core may be designed and/or provided by the integrated circuit (IC) manufacturer, or may be designed and/or provided by a third party (not the customer or the integrated circuit manufacturer), whereas the peripherals and other circuitry is typically customer specific. In many cases, the customer specific material is provided and/or designed by a different party from that which designed/provided the embedded core. Therefore, testing of integrated circuits is made increasingly difficult due to the many parties and design/test methodologies that may be involved in the design as well as the inaccessibility of circuit elements embedded deep within a microcontroller design. As more embedded core processors, or "system-on-a-chip" devices are designed, or as the level of integration increases such that many embedded cores from many providers are included on a single device, new test methods must be used.
The embedded core, which is only a portion of the total integrated circuit (IC) and is surrounded by peripherals, typically contains a plurality of input and output terminals. If the embedded core is kept as a separate structure during test pattern generation and is not bundled together with the rest of the integrated circuit logic for test pattern generation, then there is an access problem (controllability and observability) related to these plurality of input and output terminals (e.g., the input and output terminals used to test the embedded core are not accessible by the microcontroller external terminals or package pins). In most cases, the plurality of input and output terminals of the embedded core are not directly accessible by the external pins of the integrated circuit, and therefore, no direct access is available to the embedded core for providing test vectors or for other test purposes.
In addition, the complexity and transistor count of integrated circuits (ICs) has significantly increased so that simple connectivity testing and stuck-at fault testing is not adequate for modern microcontrollers. It is important that the embedded core be tested for frequency compliance, input and output terminal timing specification compliance, manufacturing induced path delay faults and transition delay faults, in addition to stuck-at faults and connectivity. It is even more advantageous if the speed path verification tasks can be performed at the operational frequency of the embedded core.
One prior art method for overcoming these design and access difficulties to the embedded core is to provide a signal path between every input terminal and every output terminal of the embedded core and a different external pin of the integrated circuit. This architecture, commonly known as "multiplexor mode", creates significant overhead in the design. In addition, routing of the signal path for "multiplexor mode" may not be possible since the number of input/output terminals on the embedded core may exceed the number of external pins of the integrated circuit (IC). In addition, this method of signal path routing can complicate the testing of the timing of the inputs and outputs to the embedded core. Furthermore, this method can result in a lower quality test program, an impact to the device die area, or an impact to the design schedule (i.e., being late to market with microcontroller design derivatives). For example, to conduct a reasonable speed or timing test would require that each signal path connection for the device package pins to the embedded core inputs and outputs be fully characterized at each operating point (temperature and supply voltage) at which the device is to be tested. This characterization will never result in a fixed propagation delay along such a signal path, but will always provide a range of possible values for that propagation delay (minimum and maximum) due to process variation in the manufacture of such products. The magnitude of the range from the minimum to maximum propagation delay for each of these signals introduces an uncertainty into the measurement or validation of embedded core input and output specifications along such propagation paths. This additional uncertainty leads to either a reduced test quality, yield reduction, or both.
Another method for overcoming the design and access difficulties is to provide a wholly serial connection whereby the embedded core input and output terminals are provided data, or are interrogated for data, respectively, by using a common-in-the-art serial scan connections. This method has the drawback of increasing test time unreasonably and not allowing at-speed testing to occur. For example, an embedded core with 100 input terminals and 100 output terminals would require 200 clock cycles to provide and interrogate one data processor cycle of terminal data. A vector set with 1000 data processor clock cycles worth of test data would be extended or multiplied by 200 and would result in an actual applied clock cost of 200,000 clock cycles. The effective frequency tested would also be reduced by 200 so a 200 MHz data processor would effectively be tested at 1 MHz.
In another prior art method, the embedded core and associated peripherals can be placed on a single chip and modeled together in such a way that the whole chip design is considered as a single entity where the embedded controller is not individually testable. For this type of design the test vectors are generated for the entire integrated circuit (IC) whereby the hierarchy of the sub-components of the microcontroller are ignored. This method is typically time inefficient since each and every integrated circuit which contains the same embedded core must be separately processed to create new test vectors whereby existing or old embedded test vectors must be discarded. This design process is generally not supported in the industry due to the intellectual property content of the embedded core data processor or of the customer supplied logic. Most suppliers of embedded cores and peripherals do not desire to disclose extensive details of there designs thereby rendering new generation of test vectors very difficult after full integration.
It would be advantageous to generate an initial set of test vectors when designing the embedded core and provide a method and system to allow the use of these initial test vectors to perform testing on the embedded core regardless of which peripherals are integrated with the embedded core. It would be advantageous to provide a method which would decouple the embedded core test process from customer specific designs and peripherals which may be located on the same substrate with the embedded core. A new isolated embedded core test process is needed since most customer specific designs use different test methodologies from that originally designed into the embedded core and may contain proprietary information which cannot be communicated to the manufacturer of the embedded core. In addition, it is important that the substrate surface area overhead associated with this embedded core test circuitry be minimized.
Therefore, the need exists for a method and system which allows for speed path and at-speed testing of embedded core designs whereby test vectors can be reused and access to the embedded core is enabled in a substrate-space efficient manner.